NonAlex
New Around Here
Hello community,
I'm trying to get RT-BE88U (running Merlin SW) connected to my LAN switch over 10G SPF+ DAC cable. Switch and DAC cable vendor is the same, so I assume it's OK there, however the link does not come up.
I'm seeing this on the router, and the line in red doesn't look good. However there are no parameters in GUI to manipulate 10G SFP+ port parameters, like autoneg parameters.. Are there any known tweaks/gotchas with using DAC cables on ASUS ?
Jul 2 11:21:35 kernel: Opticaldet Unknown Transceiver
Jul 2 11:21:35 kernel: Module Form Factor: SFP/SFP+
Jul 2 11:21:35 kernel: Module Type : UNKNOWN
Jul 2 11:21:35 kernel: Vendor Name : Amphenol
Jul 2 11:21:35 kernel: Part Number : 588680003
Jul 2 11:21:35 kernel: Part REV : E
Jul 2 11:21:35 kernel: ************************************************************************
Jul 2 11:21:35 kernel: * Opticaldet: Unknown optical module - using default configuration *
Jul 2 11:21:35 kernel: * Please make sure the optical module is correct for your connection *
Jul 2 11:21:35 kernel: ************************************************************************
Jul 2 11:21:37 kernel: SFP Module is Plugged in at Serdes address 7 core 0 lane 0
Jul 2 11:21:37 kernel: --- Step 0 powerup/reset sequence of core #0 at address 7
Jul 2 11:21:37 kernel: Toggle Serdes Core #0 PMD and uC reset.
Jul 2 11:21:37 kernel: INFO MerlinSupport::merlin_core_init(): END. Core #0 with PRTAD = 7, ln_offset_stap = 0
Jul 2 11:21:37 kernel: MerlinSupport::merlin16_serdes_init(): Step 6. Micro code load and verify
Jul 2 11:21:37 kernel: MerlinSupport::merlin_load_firmware(): ret = 0
Jul 2 11:21:37 kernel: MerlinSupport::merline_speed_set_core(): Step 7 Config Speed to 2
Jul 2 11:21:37 kernel: --- Step 8 PLL/PMD setup configuration for speed 0, mode 2.
Jul 2 11:21:37 kernel: MerlinSupport::merline_speed_set_core(): PMD Setup 50MHz, 10.3125GHz VCO programming
Jul 2 11:21:37 kernel: MerlinSupport::merlin_wait_uc_active(): wait 50us comclks for micro to be up...
Jul 2 11:21:37 kernel: MerlinSupport::merlin_wait_uc_active(): Checking uc_active passed ...
Jul 2 11:21:38 kernel: MerlinSupport::merlin_wait_uc_active(): micro is ready for command ...
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 9. Configure Core level regsiter
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 10. Set core_congif_from_pcs
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): RAM variable vco_rate is 19
Jul 2 11:21:38 kernel: MerlinSupport::merlin_cfg_core_ram_var(): program core_config_word 0x26 to ram address 0x20000200 ...
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 12. Reset Datapath (core)
Jul 2 11:21:38 kernel: MerlinSupport::merlin_reset_datapath_core(): Datapath Reset (core) in progress
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 13. Lane Configuration
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 13.a. Configure lane registers
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): RAM variable an_enabled is 0
Jul 2 11:21:38 kernel: MerlinSupport::merlin_cfg_lane_ram_var(): program lane_config_word 0x4 to ram address 0x20000300 ...
Jul 2 11:21:38 kernel: MerlinSupport::merlin_lane_config_speed(#2):
Jul 2 11:21:38 kernel: MerlinSupport::CONFIGURING FOR FORCE 1G
Jul 2 11:21:38 kernel: MerlinSupport::merlin_lane_config_speed(): Core #0 Lane #0 PMD Lock Speed Up programming
Jul 2 11:21:38 kernel: INFO MerlinSupport::merlin_lane_config_speed(): END Merlin core #0 lane #0 Initialization procedure
Jul 2 11:21:38 kernel: MerlinSupport::merlin_chk_pll_lock(): Checking Core #0 PLL Lock Status
Jul 2 11:21:38 kernel: MerlinSupport::merlin_chk_pll_lock(): PLL Locked
Jul 2 11:21:38 kernel: INFO MerlinSupport::merlin16_serdes_init(): END Merlin Initialization procedure
I'm trying to get RT-BE88U (running Merlin SW) connected to my LAN switch over 10G SPF+ DAC cable. Switch and DAC cable vendor is the same, so I assume it's OK there, however the link does not come up.
I'm seeing this on the router, and the line in red doesn't look good. However there are no parameters in GUI to manipulate 10G SFP+ port parameters, like autoneg parameters.. Are there any known tweaks/gotchas with using DAC cables on ASUS ?
Jul 2 11:21:35 kernel: Opticaldet Unknown Transceiver
Jul 2 11:21:35 kernel: Module Form Factor: SFP/SFP+
Jul 2 11:21:35 kernel: Module Type : UNKNOWN
Jul 2 11:21:35 kernel: Vendor Name : Amphenol
Jul 2 11:21:35 kernel: Part Number : 588680003
Jul 2 11:21:35 kernel: Part REV : E
Jul 2 11:21:35 kernel: ************************************************************************
Jul 2 11:21:35 kernel: * Opticaldet: Unknown optical module - using default configuration *
Jul 2 11:21:35 kernel: * Please make sure the optical module is correct for your connection *
Jul 2 11:21:35 kernel: ************************************************************************
Jul 2 11:21:37 kernel: SFP Module is Plugged in at Serdes address 7 core 0 lane 0
Jul 2 11:21:37 kernel: --- Step 0 powerup/reset sequence of core #0 at address 7
Jul 2 11:21:37 kernel: Toggle Serdes Core #0 PMD and uC reset.
Jul 2 11:21:37 kernel: INFO MerlinSupport::merlin_core_init(): END. Core #0 with PRTAD = 7, ln_offset_stap = 0
Jul 2 11:21:37 kernel: MerlinSupport::merlin16_serdes_init(): Step 6. Micro code load and verify
Jul 2 11:21:37 kernel: MerlinSupport::merlin_load_firmware(): ret = 0
Jul 2 11:21:37 kernel: MerlinSupport::merline_speed_set_core(): Step 7 Config Speed to 2
Jul 2 11:21:37 kernel: --- Step 8 PLL/PMD setup configuration for speed 0, mode 2.
Jul 2 11:21:37 kernel: MerlinSupport::merline_speed_set_core(): PMD Setup 50MHz, 10.3125GHz VCO programming
Jul 2 11:21:37 kernel: MerlinSupport::merlin_wait_uc_active(): wait 50us comclks for micro to be up...
Jul 2 11:21:37 kernel: MerlinSupport::merlin_wait_uc_active(): Checking uc_active passed ...
Jul 2 11:21:38 kernel: MerlinSupport::merlin_wait_uc_active(): micro is ready for command ...
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 9. Configure Core level regsiter
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 10. Set core_congif_from_pcs
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): RAM variable vco_rate is 19
Jul 2 11:21:38 kernel: MerlinSupport::merlin_cfg_core_ram_var(): program core_config_word 0x26 to ram address 0x20000200 ...
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 12. Reset Datapath (core)
Jul 2 11:21:38 kernel: MerlinSupport::merlin_reset_datapath_core(): Datapath Reset (core) in progress
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 13. Lane Configuration
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): Step 13.a. Configure lane registers
Jul 2 11:21:38 kernel: MerlinSupport::merline_speed_set_core(): RAM variable an_enabled is 0
Jul 2 11:21:38 kernel: MerlinSupport::merlin_cfg_lane_ram_var(): program lane_config_word 0x4 to ram address 0x20000300 ...
Jul 2 11:21:38 kernel: MerlinSupport::merlin_lane_config_speed(#2):
Jul 2 11:21:38 kernel: MerlinSupport::CONFIGURING FOR FORCE 1G
Jul 2 11:21:38 kernel: MerlinSupport::merlin_lane_config_speed(): Core #0 Lane #0 PMD Lock Speed Up programming
Jul 2 11:21:38 kernel: INFO MerlinSupport::merlin_lane_config_speed(): END Merlin core #0 lane #0 Initialization procedure
Jul 2 11:21:38 kernel: MerlinSupport::merlin_chk_pll_lock(): Checking Core #0 PLL Lock Status
Jul 2 11:21:38 kernel: MerlinSupport::merlin_chk_pll_lock(): PLL Locked
Jul 2 11:21:38 kernel: INFO MerlinSupport::merlin16_serdes_init(): END Merlin Initialization procedure