Wifi chipset design question

[tzhang4284]

Hi everyone,

I'm working on a project researching wifi technologies. I got a simple question, looking at the Asus AC-87U first look review, it seems like there is a Broadcom application processor based on an ARM core, a broadcom 2.4ghz rf chip and a 5ghz quantenna cpu + rf chip.

However, in contrast looking at the AC-68U, there is a broadcom application processor based on an ARM core, a 2.4 ghz chip and a 5ghz rf chip (EDIT: I think they're combined actually).

My question is where is the baseband processor for the broadcom RF chips? Is it implemented in the RF chips or on the application processor? Does this mean each RF chip has its own baseband processor or is that centralized in the main CPU?

Also, how are the RF chips connected to the application processor? Is it routed through an internal ethernet port or are the signals more proprietary?

Appreciate anyone who understands this that can help answer this

EDIT: Would also appreciate any insight in terms of how this applies to the Marvell chipset in the Linksys WRT1900AC. It seems like there is an application processor and a single RF chip with an independent core. http://www.marvell.com/wireless/avastar/88W8864/ and http://www.marvell.com/embedded-processors/armada-xp/

Thanks!

 

[thiggins]

RF conversion and baseband processing is generally handled in "radio" SoCs. The Broadcom BCM4360 is generally used in Broadcom-based routers. It initially handled just 5 GHz, but now is used for both 2.4 and 5 GHz since it allows QAM-256 use in 2.4 GHz. This is what provides the difference between AC1750 and AC1900 class routers.

The central processor in most designs still handles 802.3 to 802.11 conversion. But this has been offloaded to updated radio chips in Broadcom's new XStream architecture. See MU-MIMO vs. XStream: The Coming Battle For Wi-Fi Airtime
for more info.
http://www.smallnetbuilder.com/wire...s-xstream-the-coming-battle-for-wi-fi-airtime

 

[tzhang4284]

Thanks Tim - this is really helpful especially that block diagram. One question is how come for Broadcom's XStream implementation they require 3 separate radio SoCs vs. one integrated SoC. Is the constraint computing power in each of the baseband processors to handle that? Appreciate the help - this makes a lot of sense.

RF conversion and baseband processing is generally handled in "radio" SoCs. The Broadcom BCM4360 is generally used in Broadcom-based routers. It initially handled just 5 GHz, but now is used for both 2.4 and 5 GHz since it allows QAM-256 use in 2.4 GHz. This is what provides the difference between AC1750 and AC1900 class routers.

The central processor in most designs still handles 802.3 to 802.11 conversion. But this has been offloaded to updated radio chips in Broadcom's new XStream architecture. See MU-MIMO vs. XStream: The Coming Battle For Wi-Fi Airtime
for more info.
http://www.smallnetbuilder.com/wire...s-xstream-the-coming-battle-for-wi-fi-airtime

 

[sfx2000]

Hi everyone,

I'm working on a project researching wifi technologies. I got a simple question, looking at the Asus AC-87U first look review, it seems like there is a Broadcom application processor based on an ARM core, a broadcom 2.4ghz rf chip and a 5ghz quantenna cpu + rf chip.

That is correct...

However, in contrast looking at the AC-68U, there is a broadcom application processor based on an ARM core, a 2.4 ghz chip and a 5ghz rf chip (EDIT: I think they're combined actually).

Lower end BRCM basic SDK designs put the 2.4GHz MAC into the APP processor SOC, however, their higher end uses a dedicated WIFI/MAC and let's the APP SOC do the routing/switching/hotel functions...

My question is where is the baseband processor for the broadcom RF chips? Is it implemented in the RF chips or on the application processor? Does this mean each RF chip has its own baseband processor or is that centralized in the main CPU?

Talk to Broadcom - For the most part though, the baseband/RF is tightly coupled to the MAC, and the firmware for the MAC is loaded at boot time. That's about all I can say here....

Also, how are the RF chips connected to the application processor? Is it routed through an internal ethernet port or are the signals more proprietary?

Appreciate anyone who understands this that can help answer this

Depends on the design and BOM targets - many do MII, some use PCIe on the higher end - in handsets/tablets it's either SDIO or DMA - again it depends on the reference design/chipset/SDK being used.

EDIT: Would also appreciate any insight in terms of how this applies to the Marvell chipset in the Linksys WRT1900AC. It seems like there is an application processor and a single RF chip with an independent core. http://www.marvell.com/wireless/avastar/88W8864/ and http://www.marvell.com/embedded-processors/armada-xp/

Thanks!

See my deconstruction of the WRT1900ac...

sfx

 

[thiggins]

Thanks Tim - this is really helpful especially that block diagram. One question is how come for Broadcom's XStream implementation they require 3 separate radio SoCs vs. one integrated SoC. Is the constraint computing power in each of the baseband processors to handle that? Appreciate the help - this makes a lot of sense.

The BCM43602 devices allow offloading 802.3 / 802.11 conversion from the main CPU, freeing CPU for other tasks, primarily storage features.